1. Field of the Invention
The present invention relates to a semiconductor device, and in particular, to a hierarchical word line structure of a semiconductor memory device.
2. Background of the Related Art
FIG. 1 illustrates a related art hierarchical word line structure. As shown in FIG. 1, the related art hierarchical word line structure includes a plurality of word line rows R1, R2, and R3 each including sub-word line drivers SWD0 through SWD3.
For example, the first word line row R1 includes a sub-word line driver SWD0 connected with a pair of main word lines MWL0 and MWL0b. The sub-word line driver SWD0 receives a sub-word line driver enable signal SWDEN0 and drivers a sub-word line SWL0. A sub-word line driver SWD1 is connected with the main word lines MWL0 and MWL0b. The sub-word line driver SWD1 receives a sub-word line driver enable signal SWDEN1 and drives a sub-word line SWL1. A sub-word line driver SWD2 is connected with the main word lines MWL0 and MWL0b. The sub-word line driver SWD2 receives a sub-word line driver enable signal SWDEN2 and drives a sub-word line SWL2. A sub-word line driver SWD3 is connected with the main word lines MWL0 and MWL0b. The sub-word line driver SWD3 receives a sub-word line driver enable signal SWDEN3 and drives a sub-word line SWL3.
The main word lines MWL0 and MWL0b are complementary to each other. The sub-word line driver enable signals SWDEN0, SWDEN1, SWDEN2, and SWDEN3 are one bit signals of a row address. Among the above-described signals, only one signal becomes high level at a time.
The second word line row R2 includes sub-word line drivers SWD0 through SWD3 connected with a pair of main word lines MWL1 and MWL1b. In the second word line row R2, the sub-word line drivers SWD0 through SWD3 receive sub-word line driver enable signals SWDEN0 through SWDEN3 and drive sub-word lines SWL4 through SWL7. In addition, the third word line row R3 includes sub-word line drivers SWD0 through SWD3 connected with a pair of main word lines MWL2 and MWL2b for receiving sub-word line driver enable signals SWDEN0 through SWDEN3.
As shown in FIG. 2, the sub-word line driver SWD0 includes a PMOS transistor MP1 whose gate is connected with the main word line MWL0b. The source of the PMOS transistor MP1 receives the sub-word line driver enable signal SWDEN0, and the drain is connected with the sub-word line SWL0. An NMOS transistor MN1 has its gate connected with the main word line MWL0b. The drain of the NMOS transistor MN1 is connected with the sub-word line SWL0, and the source is connected to ground. An NMOS transistor MN2 has its gate connected with the main word line MWL0. The drain of the NMOS transistor MN2 receives the sub-word line driver enable signal SWDEN0, and the source is connected with the sub-word line SWL0. The sub-word line drivers SWD1 through SWD3 have the same construction as the sub-word line driver SWD0.
The operation of the related art hierarchical word line structure will now be described. When a high level signal is inputted to the main word line MWL0, the first word line row R1 is selected, and the NMOS transistor MN2 of the sub-word line driver SWD0 is turned on. The main word line MWL0 is an upper word line. Sequentially, a low level signal is applied to the main word line MWL0b, and the PMOS transistor MP1 is turned on and the NMOS transistor MN1 is turned off. When a high level sub-word line driver enable signal SWDENO is applied to the sub-word line driver SWD0, a high level signal is outputted to the sub-word line SWL0 to drive an actual word line.
However, an important factor when driving the word line is a coupling noise. The sub-word line that receives much coupling noise during the driving of the sub-word line SWL0 is sub-word line SWL2. Namely, as shown in FIG. 3, when the sub-word line SWL0 is driven by the sub-word line driver SWD0, a coupling noise can be applied to the sub-word line SWL2. The sub-word line SWL2 is driven by the sub-word line driver SWD2. At this time, the PMOS transistor MP1' and the NMOS transistor MN2' of the sub-word line driver SWD2 are turned on, while the NMOS transistor MN1' is turned off. In addition, a low level sub-word line driver enable signal SWDEN2 is applied to the source of the PMOS transistor MP1' and the drain of the NMOS transistor MN2', respectively.
However, the related art hierarchical word line structure has various disadvantages because a pair of main word lines MWL0 and MWL0b and sub-word line driver enable signals SWDEN0, SWDEN1 or SWDEN2, SWDEN3 are used. A coupling noise can appear between adjacent sub-word line drivers. Further, an additional sub-word line driver is needed relative to a word line shunt method. In addition, the layout size is disadvantageously increased.